Fin Bending Reduction Through Structure Design

ABSTRACT

A method includes etching a semiconductor substrate to form a trench between a first semiconductor strip and a second semiconductor strip. The first semiconductor strip has a first width at about 5 nm below a top of the first semiconductor strip and a second width at about 60 nm below the top of the first semiconductor strip. The first width is smaller than about 5 nm, and the second width is smaller than about 14.5 nm. The trench is filled with dielectric materials to form an isolation region, which is recessed to have a depth. A top portion of the first semiconductor strip protrudes higher than the isolation region to form a protruding fin. The protruding fin has a height smaller than the depth. A gate stack is formed to extend on a sidewall and a top surface of the protruding fin.

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the benefit of the following provisionally filedU.S. Patent application: Application No. 63/219,412, filed on Jul. 8,2021, and entitled “Fin Bending Modulation by Structure Design,” whichapplication is hereby incorporated herein by reference.

BACKGROUND

Technological advances in Integrated Circuit (IC) materials and designhave produced generations of ICs, with each generation having smallerand more complex circuits than the previous generations. In the courseof IC evolution, functional density (for example, the number ofinterconnected devices per chip area) has generally increased whilegeometry sizes have decreased. This scaling down process providesbenefits by increasing production efficiency and lowering associatedcosts

Such scaling-down has also increased the complexity of processing andmanufacturing ICs and, for these advances to be realized, similardevelopments in IC processing and manufacturing are needed. For example,Fin Field-Effect Transistors (FinFETs) have been introduced to replaceplanar transistors. The structures of FinFETs and methods of fabricatingFinFETs are being developed.

The formation of FinFETs typically involves forming semiconductor fins,forming dummy gate electrodes on the semiconductor fins, etching someportions of the semiconductor fins to form recesses, performing anepitaxy to regrow source/drain regions from the recesses, and replacingthe dummy gate electrodes with replacement gates.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1-4, 5A, 5B, 6A, 6B, 7-19, and 22-26 illustrate the perspectiveviews of intermediate stages in the formation of Fin Field-EffectTransistors (FinFETs) in accordance with some embodiments.

FIGS. 20A, 20B and 20C illustrate a top view and cross-sectional viewsof bent protruding semiconductor fins in accordance with someembodiments.

FIGS. 21A, 21B and 21C illustrate a top view and cross-sectional viewsof vertical protruding semiconductor fins in accordance with someembodiments.

FIG. 27 illustrates the determination of the bending of neighboringsemiconductor fins in accordance with some embodiments.

FIG. 28-30 illustrate the embodiments of reducing fin bending inaccordance with some embodiments.

FIG. 31 illustrates a process flow for forming semiconductor fins andFinFETs in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the invention. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are, of course, merely examples and arenot intended to be limiting. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,”“lower,” “overlying,” “upper” and the like, may be used herein for easeof description to describe one element or feature's relationship toanother element(s) or feature(s) as illustrated in the figures. Thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

A method of reducing fin bending and the corresponding structures areprovided. In accordance with some embodiments of the present disclosure,semiconductor strips are formed by etching a semiconductor substrate.Shallow Trench Isolation (STI) regions are formed between thesemiconductor strips. The STI regions are recessed, and protrudingsemiconductor fins are formed higher than the top surfaces of theremaining STI regions. The fin heights of the protruding semiconductorfins are kept to be smaller than the heights of the STI regions. Bymaintaining the fin heights to be smaller than the heights of the STIregions, the fin bending may be smaller than a critical value, so thatthe residue of dummy gate stacks and replacement gate stacks remainingin the corresponding patterning process may be eliminated. Embodimentsdiscussed herein are to provide examples to enable making or using thesubject matter of this disclosure, and a person having ordinary skill inthe art will readily understand modifications that can be made whileremaining within contemplated scopes of different embodiments.Throughout the various views and illustrative embodiments, likereference numbers are used to designate like elements. Although methodembodiments may be discussed as being performed in a particular order,other method embodiments may be performed in any logical order.

FIGS. 1-4, 5A, 5B, 6A, 6B, 7-19, and 22-26 illustrate thecross-sectional views of intermediate stages in the formation of FinField-Effect Transistors (FinFETs) in accordance with some embodimentsof the present disclosure. The corresponding processes are alsoreflected schematically in the process flow shown in FIG. 31 .

In FIG. 1 , substrate 20 is provided. The substrate 20 may be asemiconductor substrate, such as a bulk semiconductor substrate, aSemiconductor-On-Insulator (SOI) substrate, or the like. Thesemiconductor substrate 20 may be a part of wafer 10, such as a siliconwafer. Generally, an SOI substrate is a layer of a semiconductormaterial formed on an insulator layer. The insulator layer may be, forexample, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like.The insulator layer is provided on a substrate, typically a silicon orglass substrate. Other substrates such as a multi-layered or gradientsubstrate may also be used. In some embodiments, the semiconductormaterial of semiconductor substrate 20 may include silicon; germanium; acompound semiconductor including carbon-doped silicon, gallium arsenic,gallium phosphide, indium phosphide, indium arsenide, and/or indiumantimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs,AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof.

In accordance with some embodiments, substrate 20 is a siliconsubstrate. A germanium-containing semiconductor region 22B is formed asa surface region of substrate 20, and may be used for forming a p-typetransistor. In accordance with some embodiments, germanium-containingsemiconductor region 22B comprises silicon germanium (SiGe), SiGeSn,GeSn, or the like, and the germanium percentage may be in the rangebetween about 10 percent and about 40 percent. Semiconductor regions 22Aare formed at a same level as semiconductor region 22B, and may beformed of or comprise silicon. Semiconductor regions 22A may be freefrom germanium.

Pad oxide layer 24 and hard mask layer 26 are formed on semiconductorsubstrate 20. Pad oxide layer 24 may be a thin film formed of siliconoxide. In accordance with some embodiments of the present disclosure,pad oxide layer 24 is formed through a deposition process. Pad oxidelayer 24 acts as an adhesion layer between semiconductor substrate 20and hard mask layer 26. Pad oxide layer 24 may also act as an etch stoplayer for etching hard mask layer 26. In accordance with someembodiments of the present disclosure, hard mask layer 26 is formed ofsilicon nitride, for example, using Atomic Layer Deposition (ALD),Low-Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced ChemicalVapor Deposition (PECVD), or the like. A patterned photo resist 28 isformed on hard mask layer 26. The respective process is illustrated asprocess 202 in the process flow 200 as shown in FIG. 31 .

Next, hard mask layer 26 is patterned in an etching process using thepatterned photo resist 28 as an etching mask, so that hard masks 26′ areformed, as shown in FIG. 2 . The respective process is illustrated asprocess 204 in the process flow 200 as shown in FIG. 31 . Pad oxidelayer 24 is then etched, and the remaining portions of pad oxide layerare denoted as pad oxide layers 24′. Semiconductor substrate 20 is thusexposed. Photo resist 28 is removed, either before or after thepatterning of pad oxide layer 24. The resulting structure is shown inFIG. 2 .

Referring to FIG. 3 , the exposed semiconductor substrate 20 is etchedin an anisotropic etching process, forming trenches 32. The respectiveprocess is illustrated as process 206 in the process flow 200 as shownin FIG. 31 . The portions of semiconductor substrate 20 betweenneighboring trenches 32 are referred to as semiconductor strips 30(including 30A and 30B) hereinafter. Trenches 32 may have the shape ofstrips (when viewed in the top view of wafer 10) that are parallel toeach other, and trenches 32 are closely located from each other. Inaccordance with some embodiments of the present disclosure, the aspectratio (the ratio of depth to width) of trenches 32 is greater than abut7, and may be greater than about 10. Semiconductor strips 30 includesemiconductor strips 30A, which may include silicon regions 22A.Semiconductor strips 30 further include semiconductor strips 30B, whichmay include silicon strips as lower portions, and germanium-containingregion strips 22B (which are the remaining portions ofgermanium-containing region 22B) as upper portions. After the formationof trenches 32, hard masks 26′ may be removed, as shown in FIG. 3 , ormay have some portions remaining.

FIGS. 4 and 5A illustrate the patterning (cutting) of semiconductorstrips 30. Referring to FIG. 4 , an etching mask 34, which may be atri-layer, is formed. The respective process is illustrated as process208 in the process flow 200 as shown in FIG. 31 . Etching mask 34 mayinclude bottom layer (also sometimes referred to as an under layer)34BL, middle layer 34ML over bottom layer 34BL, and top layer (alsosometimes referred to as an upper layer) 34TL over middle layer 34ML. Inaccordance with some embodiments, bottom layer 34BL and top layer 34TLare formed of photo resists, with the bottom layer 34BL beingcross-linked already. Middle layer 34ML may be formed of an inorganicmaterial, which may be a nitride (such as silicon nitride), anoxynitride (such as silicon oxynitride), an oxide (such as siliconoxide), or the like. Middle layer 34ML has a high etching selectivityrelative to top layer 34TL and bottom layer 34BL, and hence top layer34TL may be used as an etching mask for patterning middle layer 34ML,and middle layer 34ML may be used as an etching mask for patterningbottom layer 34BL. Top layer 34TL is patterned to form openings 37.

The etching mask 34 as shown in FIG. 4 is used to cut semiconductorstrips 30, wherein anisotropic etching processes are performed to etchmiddle layer 34ML, bottom layer 34BL, hard masks 26′ (if any remaining)and pad oxide layers 24′, and semiconductor strips 30. The respectiveprocess is illustrated as process 210 in the process flow 200 as shownin FIG. 31 . The example cut semiconductor strips 30B are illustrated inFIG. 5A. FIG. 5B illustrates a cross-section 5B-5B of the structureshown in FIG. 5A, wherein one semiconductor strip 30A is illustrated.The cross-sectional views of semiconductor strips 30B are similar tothat of semiconductor strips 30A, except the top portions ofsemiconductor strips 30B may be germanium-containing regions.

FIGS. 6A, 6B, 7, and 8 illustrate the formation of STI regions inaccordance with some embodiments. Referring to FIG. 6A, liner dielectric36 is formed at the bottoms of trenches 32 and extending on thesidewalls of semiconductor strips 30. The respective process isillustrated as process 212 in the process flow 200 as shown in FIG. 31 .Liner dielectric 36 may be a conformal layer, whose horizontal portionsand vertical portions have thicknesses close to each other, for example,with a thickness variation smaller than 20 percent or 10 percent. Inaccordance with some embodiments of the present disclosure, linerdielectric 36 is formed using a deposition method such as Chemical VaporDeposition (CVD), Sub Atmospheric Chemical Vapor Deposition (SACVD),Atomic Layer Deposition (ALD), or the like. Liner dielectric 36 may beformed of or comprises silicon oxide, silicon nitride, or compositelayers thereof. FIG. 6B illustrates a cross-section 6B-6B of thestructure shown in FIG. 6A.

Dielectric material 38 is then deposited to fill the remaining portionsof trenches 32, resulting in the structure shown in FIG. 7 . Therespective process is illustrated as process 214 in the process flow 200as shown in FIG. 31 . The deposition method of dielectric material 38may be selected from Flowable Chemical Vapor Deposition (FCVD), spin-oncoating, CVD, ALD, High-Density Plasma Chemical Vapor Deposition(HDPCVD), LPCVD, and the like. In accordance with some embodiments inwhich FCVD is used, a silicon-and-nitrogen-containing precursor (forexample, trisilylamine (TSA) or disilylamine (DSA)) is used, and hencethe resulting dielectric material 38 is flowable. In accordance withalternative embodiments of the present disclosure, the flowabledielectric material 38 is formed using an alkylamino silane basedprecursor. The deposition temperature may be in the range between about300° C. and about 1,100° C. The pressure of the precursors may be in therange between about 0.01 Torr and about 760 Torr. The deposition timemay be shorter than 10 hours.

After dielectric material 38 is deposited, an annealing/curing processis performed, which converts flowable dielectric material 38 into asolid dielectric material. The solidified dielectric material 38 is alsoreferred to as dielectric material 38. In accordance with someembodiments of the present disclosure, the annealing process isperformed in an oxygen-containing environment. The annealing temperaturemay be higher than about 200° C., for example, in a range between about200° C. and about 700° C. During the annealing, an oxygen-containingprocess gas is conducted into the process chamber in which wafer 10 isplaced. The oxygen-containing process gas may include oxygen (O₂), ozone(O₃), or combinations thereof. Steam (H₂O) may also be used, and may beused along with or without oxygen (O₂) or ozone. As a result of theannealing process, dielectric layer 38 is cured and solidified.

A planarization process such as a Chemical Mechanical Polish (CMP)process or a mechanical grinding process is then performed, as shown inFIG. 8 . The respective process is illustrated as process 216 in theprocess flow 200 as shown in FIG. 31 . STI regions 40 are thus formed,which include the remaining portions of liner dielectric 36 anddielectric material 38. Hard masks 26′ (if remaining) or pad oxidelayers 24′ may be used as the CMP stop layer, and hence the top surfaceof STI regions 40 are level with the top surfaces of hard masks 26′ orpad oxide layers 24′.

FIG. 9 illustrates the recessing of STI regions 40, which recessingprocess is performed, for example, through an isotropic etching process.The respective process is illustrated as process 218 in the process flow200 as shown in FIG. 31 . The height of the remaining STI regions 40 maybe in the range between about 10 nm and about 80 nm. The etching processmay be a dry etching process, which may be performed using the mixtureof NF₃ and NH₃ or the mixture of HF and NH₃. Alternatively, the etchingprocess may be a wet etching process, which may be performed usingdiluted HF solution as the etchant.

FIG. 10 illustrates the formation and the planarization of pad layer 42.The respective process is illustrated as process 220 in the process flow200 as shown in FIG. 31 . In accordance with some embodiments, pad layer42 comprises an oxide layer (such as a silicon oxide layer), a nitridelayer (such as a silicon nitride layer), or a composite layer includingan oxide layer, and a nitride layer overlying or underlying the oxidelayer. The pad layer 42 fills the recesses formed due to the recessingof STI regions 40. Next, a planarization process is performed. Theplanarization process may be performed using semiconductor strips 30 asbeing a CMP stop layer. Accordingly, after the planarization process,semiconductor strips 30 are exposed, and the top surfaces ofsemiconductor strips 30 are level with the top surface of pad layer 42.

Pad layer 42 is then removed. Next, referring to FIG. 11 , STI regions40 are recessed to form trenches 44. The respective process isillustrated as process 222 in the process flow 200 as shown in FIG. 31 .The top portions of semiconductor strips 30 thus protrude higher thanthe top surfaces of the remaining portions of STI regions 40 to formprotruding fins 48 (including 48A and 48B). The etching may be performedusing a dry etching process, wherein HF and NH₃, for example, are usedas the etching gases. During the etching process, plasma may begenerated. Argon may also be included. In accordance with alternativeembodiments of the present disclosure, the recessing of STI regions 40is performed using a wet etching process. The etching chemical mayinclude HF, for example. Protruding fins 48 include protruding fins 48A,which are silicon fins, and protruding fins 48B, which are or comprisesilicon germanium fins.

Protruding fins 48 may suffer from bending. In accordance with someembodiments, processes are selected to reduce the bending of protrudingfins 48. Processes may also be controlled so that some portions (such asportions 48′ in FIG. 28 ) of protruding fins 48 are laterally expanded,and are at selected positions, to strengthen the protruding fins 48, andto reduce the bending of protruding fins 48. The details for reducingthe bending are discussed subsequently with reference to FIGS. 27through 30 .

FIG. 27 illustrates the determination of the magnitude of the bending ofprotruding fins 48. The magnitude of the bending is also referred to asthe bending value of protruding fins 48. Two semiconductor strips 30 areneighboring each other. Protruding fins 48 are the top portions of thesemiconductor strips 30, which top portions are higher than the topsurfaces of STI regions 40. The left and right semiconductor strips 30have middle lines 102A and 102B, respectively. When protruding fins 48are bent, the spacings between middle lines 102A and 102B at higherlevels are different from the spacings between middle lines 102A and102B at lower levels. Since the top portions of protruding fins 48 arerounded, the top pitch P_(T) of protruding fins 48, which top pitch isthe spacing between middle lines 102A and 102B, is measured at a levelthat is 5 nm below the tops of protruding fins 48. The bottom pitchP_(B) of protruding fins 48 is measured at the bottoms of protrudingfins 48. Alternatively stated, the bottom pitch P_(B) may be measured atto the top of STI regions 40. The difference |(P_(T)−P_(B))|, which isthe absolute value of the difference between pitches P_(T) and P_(B), isreferred to as being the bending (value) B of protruding fins 48. Thebending value B may also be calculated as|[(W_(TL)+W_(TR))/2+S_(TLR)]−[(W_(BL)+W_(BR))/2+S_(BLR)]|, whereinwidths W_(TL) and W_(TR) are the top widths (measured at 5 nm below top)of protruding fins 48, and widths W_(BL) and W_(BR) are the bottomwidths of protruding fins 48. Spacing S_(TLR) is the top spacing betweenleft protruding fin 48 and right protruding fin 48. Spacing S_(BLR) isthe bottom spacing between left protruding fin 48 and right protrudingfin 48.

It has been found that bending value B equal to 4 nm is a critical valuesignificantly affecting the resulting device. For example, as will bediscussed referring to FIGS. 20A, 20B, and 20C, when bending value B isgreater than 4 nm, residues 54″ (FIG. 20B) may be left unremoved when adummy gate electrode layer is patterned to form a dummy gate. Also, inthe subsequent etching of replacement gate stacks, residues of thereplacement gate stacks may also be left when bending value B is greaterthan 4 nm. These residues may electrical short the features on oppositesides of the residues. When bending value B is smaller than 4 nm, on theother hand, no residues have been found. Accordingly, bending value B isto be maintained to be lower than 4 nm. Also, when ratio B/H is smallerthan 0.1, no residues are found, wherein H (FIG. 27 ) is the height ofprotruding fins 48. Throughout the description, the bending value B thatdo not result in residue is referred to as a within-specificationbending value B, which is smaller than 4 nm, and thewithin-specification bending value B satisfies the requirement(B/H<0.1).

FIG. 28 illustrates the schematic view of a structure, which includessemiconductor strips 30, STI regions 40, and gate dielectrics 52′/80,which may be dummy gate dielectrics 52′ or replacement gate dielectric80 (FIG. 26 ). It has also been found that how much of the semiconductorstrips 30 are embedded in STI regions 40 (and how much of thesemiconductor strips 30 protrude over STI regions 40) affect the bendingvalue B of protruding fins 48. When more of semiconductor strips 30 areembedded in, rather than protruding out of, STI regions 40, the bendingvalue B is to be smaller than the within-specification bending value B.Alternatively stated, when ratio H/D is smaller than 1, bending value Bwill be smaller than the within-specification bending value B.Throughout the description, when the bending value B is describedsmaller than 4 nm, the bending value B may be 0 nm, or may be a non-zerovalue, for example, greater than about 0.5 nm or greater than about 1nm. Accordingly, the bending value B may be in the range between about 0nm, or in the range between about 1 nm and about 4 nm. Conversely, whenthe heights H of protruding fins 48 is equal to or greater than thedepth D of the adjoining STI region(s) 40 (so that H/D is equal to orgreater than 1), the bending value B is greater than thewithin-specification bending value B.

The ratio H/D may also be in the range between about 0.2 and about 0.9in order to maintain the bending value B to be within specification withadequate process margin. Ratio H/D may also be in the range of about 0.2and about 0.5 to further reduce the bending, for example, whensemiconductor strips 30 are very narrow. In accordance with someembodiments of the present disclosure, when ratio H/D is smaller than1.0 (for example, when depth D is in the range between about 55 nm andabout 80 nm, and when height H is in the range between about 10 nm andabout 33 nm), the bending value B is within specification. The ratio B/Hmay be smaller than about 0.1. The reduction of ratio H/D may alsoeffectively reducing bending value B for very thin and tall fins. Forexample, the thin-and-tall fins in accordance with the embodiments ofthe present disclosure may have width W_(a,5) smaller than 5 nm,W_(a,20) smaller than 6.5 nm, W_(a,40) smaller than 8.3 nm, and W_(a,60)smaller than 14.5 nm. Widths W_(a,5), W_(a,20), W_(a,40), and W_(a,60)are measure at levels 5 nm, 20 nm, 40 nm, and 60 nm, respectively, belowthe tops of protruding fins 48. In accordance with some embodiments, finheights H may be in the range between about 40 nm and about 80.

As shown in FIGS. 28, 29, and 30 , in accordance with some embodiments,protruding fins 48 may have portions 48′ that are laterally expanded tobe wider than the overlying and underlying portions of protruding fins48. The formation of wider portions 48′ may be achieved by adjustingprocess conditions such as by adjusting the bias power in the processshown in FIG. 5A. For example, when etching the portions ofsemiconductor substrate on opposite sides of laterally-expanded portions48′, lower bias power may be used, while greater bias power may be usedbefore and after forming laterally-expanded portions 48′.Laterally-expanded portions 48′ may strengthen the protruding fins 48 toreduce the bending. Furthermore, the position of laterally-expandedportions 48′ also affects the bending. In accordance with someembodiments, laterally-expanded portions 48′ include some portionshigher than top point 40 _(T) (FIG. 28 ) of STI region 40. The bottomsof laterally-expanded portions 48′ may be level with the top point 40_(T), or slightly lower than top point 40 _(T).

FIG. 29 illustrates an embodiment in which two STI regions 40 are nextto each other, with semiconductor strips 30 and protruding fins 48 beingon the opposing sides of the STI regions 40. In accordance with someembodiments, to ensure the three illustrated protruding fins 48 all havebending value B to be within specification, both of ratios H1/D1 andH2/D2 are smaller than 1. Otherwise, assuming H1/D1 is greater than 1(for example, when D1 is in the range between about 10 nm and about 30nm), and H2/D2 is smaller than 1 (for example, when D2 is in the rangebetween about 55 nm and about 80 nm), bending value B measured betweenthe left and the middle protruding fin 48 may be greater than 4 nm(which is out of specification), and the bending value B measuredbetween the middle and the right protruding fins 48 may be smaller than4 nm (within specification). Again, the bending value B may be, or maynot be, a non-zero value, for example, in the range between about 1 nmand about 4 nm. Accordingly, for a bending value B of a protruding fin48 to have bending value B within specification, both of H1/D1 and H2/D2are designed as being smaller than 1, and may be in the range betweenabout 0.2 and about 0.9. Furthermore, the width W2 may be greater thanwidth W1, for example, with ratio W2/W1 being greater than 2 or 3. Thismay further worsen the bending of the protruding fin 48 in the middle.With both of H1/D1 and H2/D2 being smaller than 1, the bending may bereduced. In FIG. 30 , ratios D3/D1, D3/D2, D4/D1, and D4/D2 may begreater than about 1.2, greater than about 1.5, or greater than about 2without affecting bending value B to be out of specification.

FIG. 30 illustrates an embodiment in which two STI regions 40 are nextto each other, with semiconductor strips 30 and protruding fins 48 beingon opposing sides of the STI regions. It is also found that when morethan two protruding fins 48 are formed adjacent to each other, thespacings of a fin from its neighboring fins may be designed uniform andhave values close to each other in order to reduce fin bending. Forexample, in FIG. 30 , spacings S_(a) and S_(b) are marked. When spacingsS_(a) and S_(b) are substantially equal to each other, for example, whenthe difference in spacing |(S_(a)−S_(b))| is smaller than 4 nm, the finbending value B of the protruding fins are within specification,regardless of whether the ratios H1/D1 and/or H2/D2 are greater than 1or smaller than 1, and B/H1 and B/H2 may be kept to be smaller than 0.1.Alternatively stated, when either one or both of the requirements(H/D<1) and (|(S_(a)−S_(b))|<4 nm) is satisfied, the correspondingprotruding fin 48 will have within-specification bending value B.

Furthermore, the depth D2 may be greater than depth D1, for example,with ratio D2/D1 being greater than about 1.2, greater than about 1.5,or greater than about 2, or greater than about 5. Also, ratio(H2+D2)/(H1+D1) may also be greater than about 1.2, greater than about1.5, or greater than about 2, wherein values (H2+D2) and (H1+D1) are thecorresponding depths of trenches 32 (FIG. 5 ), in which STI regions 40are formed. This may further worsen the bending of the protruding fin 48in the middle due to different stresses applied by the STI regions 40from the opposite sides. With both of both of the requirements (H/D<1)and (|(S_(a)-S_(b))|<4 nm) being satisfied, the bending may be reduced.

In accordance with some embodiments, to ensure all of the protrudingfins in an entire die and wafer have within-specification bending, allof the fins throughout the entire die and wafer meet at least one, orboth, of requirements (H/D<1) and (|(S_(a)—S_(b))|<4 nm) in anycombination. For example, in a device die, a first plurality ofprotruding fins may have within-specification bending because theysatisfy the requirement (H/D<1), a second plurality of fins may havewithin-specification bending because they satisfy the requirement(|(S_(a)−S_(b))|<4 nm), and a third plurality of fins havewithin-specification bending because they satisfy both of therequirements (H/D<1) and (|(S_(a)−S_(b))|<4 nm). There will not beprotruding fins in the die and wafer that fail to meet at least one ofthe requirements (H/D<1) and (|(S_(a)—S_(b))|<4 nm). Again, the bendingvalue B may be, or may not be, a non-zero value, for example, in therange between about 1 nm and about 4 nm.

FIG. 12 illustrates the deposition of silicon capping layer 50 and dummygate dielectric layer 52 over silicon capping layer 50. The respectiveprocess is illustrated as process 224 in the process flow 200 as shownin FIG. 31 . In accordance with some embodiments, silicon capping layer50 is formed through deposition. In accordance with some embodiments,silicon capping layer 50 is deposited using a silicon-containingprecursor comprising silane, disilane, dichlorosilane (DCS),Trichlorosilane (SiHCl₃), Chlorosilane (SiH₃Cl), or the like. Thedeposition may be performed through a conformal deposition process suchas a CVD process or an ALD process. When ALD is used, the precursors asaforementioned may be pulsed and purged, followed by the pulsing andpurging of another process gas such as H₂. The two types of gases arepulsed and purged alternatingly to increase the thickness of the siliconcapping layer 50 to a desirable thickness. The ALD process may be athermal ALD process, which is performed, for example, at a temperaturein a range between about 350° C. and about 500° C. When CVD is used,precursors such as silane, disilane, HMDS, DCS, H₂, and/or the like asaforementioned, may be used.

Dummy gate dielectric layer 52 is formed simultaneously as the formationof the gate dielectric of an Input-Output (IO) device, and hence isalternatively referred to as an IO dielectric. In accordance with someembodiments, dummy gate dielectric layer 52 comprises silicon oxide.

FIG. 13 illustrates the formation of dummy gate electrode layer 54. Therespective process is illustrated as process 226 in the process flow 200as shown in FIG. 31 . In accordance with some embodiments, dummy gateelectrode layer 54 comprises polysilicon or amorphous silicon. Theformation may be performed using precursors including silane, disilane,dichlorosilane (DCS), Trisilane (Si₃H8), high-order Silane(Si_(n)H_(2n+2), n>3), Dimethylaminosilane (SiH₃[N(CH₃)₂], DMAS),Ethylmethylaminosilane (SiH₃[N(CH₃C₂H₅)], EMAS), Diethylaminosilane(SiH₃[N(C₂H₅)₂], DEAS), Ethylisopropylaminosilane (SiH₃[N(C₂H₅C₃H₇)],EIPAS), Diisopropylaminosilane (SiH₃[N(C₃H₇)₂], DIPAS),Dipropylaminosilane (SiH₃[N(C₃H₇)₂], DPAS), Dichlorosilane (SiH₂Cl₂),Trichlorosilane (SiHCl₃), Chlorosilane (SiH₃Cl), or the like. Thepressure of the precursor may be in the range between about 0.1 Torr andabout 5 Torr. The temperature for growing dummy gate electrode layer 54may be in the range between about 100° C. and about 750° C. Depending onthe temperature, the growth rate of dummy gate electrode layer 54, andother process conditions, dummy gate electrode layer 54 may be anamorphous silicon layer, a polysilicon layer, or the mixture thereof.The deposition process may also be performed using CVD, ALD, or thelike. The top surface of the deposited dummy gate electrode layer 54 ishigher than the top surfaces of protruding fins 48. A planarizationprocess may then be performed to level the top surface of dummy gateelectrode layer 54.

In accordance with some embodiments, a pad layer 56, which may be formedof silicon nitride, silicon oxide, or the like, may be deposited on thetop surface of dummy gate electrode layer 54. The pad layer 56 is usedfor performing other processes, which are not discussed herein. Forexample, polysilicon layer 57 may be deposited on the pad layer 56.Next, polysilicon layer 57 and the pad layer 56 are removed. Dummy gateelectrode layer 54 may then be recessed (thinned) in accordance withsome embodiments to a desirable thickness. The resulting structure isshown in FIG. 14 . In accordance with alternative embodiments, pad layer56 is not deposited, and the dummy gate electrode layer 54 is polishedto the desirable thickness.

FIGS. 15 through 19 illustrate the formation of dummy gate stacksthrough a double-patterning process. It is appreciated that depending onthe requirement of the device, single patterning processes or quadruplepatterning processes may also be used.

Referring to FIG. 15 , hard mask layers are formed. The hard mask layersmay include an oxide layer, a nitride layer, or the like, or compositelayers thereof. In accordance with some embodiments, hard mask layersincludes layers 58 and 60, which may include a silicon oxide layer and asilicon nitride layer over the silicon oxide layer.

Mandrel layer 62 is deposited over hard mask layers 58 and 60. Mandrellayer 62 may be formed of or comprise amorphous silicon, amorphouscarbon, tin oxide, or the like. Etching mask 64, which may be atri-layer, is formed over mandrel layer 62. Etching mask 64 may includebottom layer 64BL, middle layer 64ML over bottom layer 64BL, and toplayer 64TL over middle layer 64ML. In accordance with some embodiments,bottom layer 64BL and top layer 648TL are formed of photo resists, withthe bottom layer 64BL being cross-linked. Middle layer 64ML may beformed of an inorganic material, which may be a nitride (such as siliconnitride), an oxynitride (such as silicon oxynitride), an oxide (such assilicon oxide), or the like. Top layer 64TL is patterned.

A plurality of etching processes are then performed using the etchingmask 64 to define patterns, so that mandrel layer 62 is etched to formmandrel 62′. The respective process is illustrated as process 228 in theprocess flow 200 as shown in FIG. 31 . After the patterning process, theremaining portions of etching mask 64 are removed. The resultingstructure is shown in FIG. 16 .

Referring to FIG. 17 , spacer layer 66 is deposited. In accordance withsome embodiments, spacer layer 66 is formed of or comprises ametal-containing material such as a metal oxide or a metal nitride, forexample, titanium oxide, titanium nitride, or the like. Spacer layer 66is formed as a conformal spacer, which includes vertical portions on thesidewalls of mandrel 62′, top horizontal portions on top of mandrel 62′,and bottom horizontal portions on top of hard mask 60.

An anisotropic etching process is then performed to remove the tophorizontal portions and the bottom horizontal portions, and leaving thevertical portions, which are spacers 66′, as shown in FIG. 18 . Therespective process is illustrated as process 230 in the process flow 200as shown in FIG. 31 . In accordance with some embodiments, theanisotropic etching process is performed using etching gases such asCl₂, HBr, CH₄, or the like, or combinations thereof. Carrier gases suchas N₂, argon, or the like, may also be added into the etching gases.After the etching process, mandrel 62′ is removed through an etchingprocess.

In a subsequent process, hard masks 60 and 58 are patterned inanisotropic etching processes, with mandrels 62′ being used as anetching mask. The remaining hard masks 60′ and 58′ are shown in FIG. 19. Hard masks 60′ and 58′ are then used as an etching mask to etch dummygate electrode layer 54, and to form dummy gate electrodes 54′. Therespective process is illustrated as process 232 in the process flow 200as shown in FIG. 31 . Gate dielectric layer 52 is also etched to formdummy gate dielectrics 52′. The etching of silicon in dummy gateelectrode layer may be performed at a temperature in the range betweenabout 100° C. and about 700° C. The etching gas may include fluorine(F₂), Chlorine (Cl₂), hydrogen chloride (HCl), hydrogen bromide (HBr),bromine (Br₂), etc., SiH₂Cl₂, or combinations thereof. The pressure ofthe etching gas may be in the range between about 0.1 Torr and about 200Torr. The carrier gas may include H₂ and/or N₂, which may have flowrates of lower than about 20 slm.

Dummy gate stacks 68 are thus formed. Dummy gate stacks 68 includesdummy gate electrodes 54′ and dummy gate dielectrics 52′, which are theremaining portions of dummy gate electrode layer 54 and dummy gatedielectric 52, respectively. Dummy gate stacks 68 may further includeshard masks 58′ and 60′, which are the remaining portions of thepatterned hard mask layers 58 and 60.

FIGS. 20A, 20B, and 20C illustrate a top view and two cross-sectionalviews of the structure shown in FIG. 19 , wherein protruding fins 48 arebent, and have bending value B being out of specification (greater than4 nm). FIG. 20A illustrates the top view of three protruding fins 48.FIGS. 20B and 20C illustrate the reference cross-sections 20B-20B and20C-20C, respectively, in FIG. 20A. Silicon capping layer 50 is notillustrated separately since it may be merged with the protruding fins48 and the bulk portion of the semiconductor substrate 20. Referring toFIG. 20B. The left fin and the right fin bend outwardly relative to eachother, and the middle fin and the right fin bend inwardly relative toeach other. In the cross-section as shown in FIG. 20B, the majority ofdummy gate electrode layer 54 has been removed. Due to the bending ofprotruding fins 48, however, some portions of dummy gate electrode layer54 are shadowed by the bending protruding fins 48, and are not removed,which are shown as dummy gate residues 54″.

FIGS. 21A, 21B, and 21C illustrate a top view and two cross-sectionalview of the structure shown in FIG. 19 in accordance with theembodiments of the present disclosure, in which protruding fins 48 havebending value B within specification. Alternatively stated, protrudingfins 48 are vertical or substantially vertical, with bending value Bsmaller than 4 nm. FIG. 21A illustrates the top view of three protrudingfins 48. FIGS. 21B and 21C illustrate the reference cross-sections21B-21B and 21C-21C, respectively, in FIG. 21A. In the cross-section asshown in FIG. 21B, the entirety of dummy gate electrode layer 54 hasbeen removed, and there is no residue left.

Referring to FIG. 22 , gate spacers 70 are formed on the sidewalls ofdummy gate stacks 68. In accordance with some embodiments of the presentdisclosure, gate spacers 70 are formed of a dielectric material(s) suchas silicon nitride, silicon oxy-carbo-nitride, or the like, and may havea single-layer structure or a multi-layer structure including aplurality of dielectric layers.

Next, some portions of protruding fins 48 as shown in FIG. 19 , whichportions are not covered by dummy gate stacks 68 and gate spacers 70,are recessed in an etching process, resulting in the structure shown inFIG. 22 . The respective process is illustrated as process 234 in theprocess flow 200 as shown in FIG. 31 . The recessing may be anisotropic,and hence the portions of protruding fins 48 directly underlying dummygate stacks 68 and gate spacers 70 are protected, and are not etched.The top surfaces of the recessed semiconductor strips 30 may be lowerthan the top surfaces 40A of STI regions 40 in accordance with someembodiments. Recesses 72 are accordingly formed. Recesses 72 comprisesome portions located on the opposite sides of dummy gate stacks 68, andsome portions between the remaining portions of protruding fins 48.

Next, epitaxy regions (source/drain regions) 74 are formed byselectively growing (through epitaxy) a semiconductor material inrecesses 72, resulting in the structure in FIG. 23 . The respectiveprocess is illustrated as process 236 in the process flow 200 as shownin FIG. 31 . Depending on whether the resulting FinFET is a p-typeFinFET or an n-type FinFET, a p-type or an n-type impurity may bein-situ doped with the proceeding of the epitaxy. For example, when theresulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB),silicon boron (SiB), GeB, or the like may be grown. Conversely, when theresulting FinFET is an n-type FinFET, silicon phosphorous (SiP), siliconcarbon phosphorous (SiCP), or the like may be grown. In accordance withalternative embodiments of the present disclosure, epitaxy regions 74comprise III-V compound semiconductors such as GaAs, InP, GaN, InGaAs,InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, ormulti-layers thereof. After Recesses 72 are filled with epitaxy regions74, the further epitaxial growth of epitaxy regions 74 causes epitaxyregions 74 to expand horizontally. The further growth of epitaxy regions74 may also cause neighboring epitaxy regions 74 to merge with eachother.

FIG. 24 illustrates a perspective view of the structure after theformation of Contact Etch Stop Layer (CESL) 76 and Inter-LayerDielectric (ILD) 78. The respective process is illustrated as process238 in the process flow 200 as shown in FIG. 31 . CESL 76 may be formedof silicon oxide, silicon nitride, silicon carbo-nitride, or the like,and may be formed using CVD, ALD, or the like. ILD 78 may include adielectric material formed using, for example, FCVD, spin-on coating,CVD, or another deposition method. ILD 78 may be formed of anoxygen-containing dielectric material, which may be a silicon-oxidebased material such as Tetra Ethyl Ortho Silicate (TEOS) oxide,Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-DopedPhospho-Silicate Glass (BPSG), or the like. A planarization process suchas a CMP process or a mechanical grinding process may be performed tolevel the top surfaces of ILD 78, dummy gate stacks 68, and gate spacers70 with each other.

Hard masks 58′ and 60′, dummy gate electrodes 54′, and dummy gatedielectric layers 52′ are then removed, forming trenches between gatespacers 70, followed by the formation of replacement gate stacks 84. Therespective process is illustrated as process 240 in the process flow 200as shown in FIG. 31 . Gate stacks 84 include gate dielectrics 80 andgate electrodes 82. Gate dielectric 80 may include an Interfacial Layer(IL, not shown separately) and a high-k dielectric layer (not shown).The IL is formed on the exposed surfaces of protruding fins 48, and mayinclude an oxide layer such as a silicon oxide layer, which is formedthrough the thermal oxidation of protruding fins 48, a chemicaloxidation process, or a deposition process. The high-k dielectric layerincludes a high-k dielectric material such as hafnium oxide, lanthanumoxide, aluminum oxide, zirconium oxide, or the like. The dielectricconstant (k-value) of the high-k dielectric material is higher than 3.9,and may be higher than about 7.0. In accordance with some embodiments ofthe present disclosure, the high-k dielectric layer is formed using ALD,CVD, or the like.

In accordance with some embodiments, gate electrodes 82 includes stackedlayers, which may include a diffusion barrier layer (a capping layer),and one or more work-function layer over the diffusion barrier layer.The diffusion barrier layer may be formed of titanium nitride, which may(or may not) be doped with silicon. The work-function layer determinesthe work-function of the gate electrode, and includes at least onelayer, or a plurality of layers formed of different materials. Thespecific material of the work-function layer may be selected accordingto whether the respective FinFET is an n-type FinFET or a p-type FinFET.A metal-filling region is then formed on the stacked layers and fullyfilling the trenches left by the removed dummy gate stacks. Themetal-filling region may be formed of or comprise cobalt, tungsten,alloys thereof, or other metal or metal alloys.

Next, as shown in FIG. 25 , a planarization process such as a CMPprocess or a mechanical grinding process is performed, so that the topsurface of gate stacks 84 are coplanar with the top surface of ILD 78.In a subsequent process, gate stacks 84 are etched back, resulting inrecesses being formed between opposite gate spacers 70. Next, as shownin FIG. 26 , hard masks 86 are formed over replacement gate stacks 84.In accordance with some embodiments of the present disclosure, theformation of hard masks 86 includes a deposition process to form ablanket dielectric material, and a planarization process to remove theexcess dielectric material over gate spacers 70 and ILD 78. Hard masks86 may be formed of silicon nitride, for example, or other likedielectric materials.

In accordance with some embodiments, gate isolation regions 85 may beformed to cut gate stacks 84 into discrete portions. The formation ofgate isolation regions 85 may include etching gate stacks 84 to formopenings, which separate the otherwise long gate stacks 84 into smallerportions. The openings are filled with a gate dielectric material(s) toelectrically isolate the gate stacks. In the etching of gate stacks 84,if protruding fins 48 are bent with out-of-specification bending valueB, the etched gate stacks 84 may also have residues, which mayelectrically inter-couple the portions of gate stacks 84 that areintended to be electrically isolated. Accordingly, the embodiments ofthe present disclosure also solve this problem.

FIG. 26 further illustrates some of the features formed in subsequentprocesses, which may include source/drain silicide regions 88,source/drain contact plugs 90. FinFETs 94 are thus formed.

The embodiments of the present disclosure have some advantageousfeatures. By controlling the ratio of the heights of protruding fins tothe depths of STI regions, and/or controlling the uniformity of thespacings between neighboring protruding fins, the bending of protrudingfins is controlled. The problems resulted from bent protruding fins arethus solved.

In accordance with some embodiments of the present disclosure, a methodcomprises etching a semiconductor substrate to form a first trenchbetween a first semiconductor strip and a second semiconductor strip,and a second trench between the second semiconductor strip and a thirdsemiconductor strip, wherein the second trench is deeper than the firsttrench; filling the first trench and the second trench to form a firstisolation region between the first semiconductor strip and the secondsemiconductor strip, and a second isolation region between the secondsemiconductor strip and the third semiconductor strip; recessing thefirst isolation region and the second isolation region, wherein a firstprotruding fin, a second protruding fin, and a third protruding fin areformed as top portions of the first semiconductor strip, the secondsemiconductor strip, and the third semiconductor strip, wherein thefirst protruding fin is spaced apart from the second protruding fin by afirst spacing, and the second protruding fin is spaced apart from thethird protruding fin by a second spacing substantially equal to thefirst spacing, wherein bending values of the first protruding fin, thesecond protruding fin, and the third protruding fin are smaller thanabout 4 nm; forming a gate stack on the second protruding fin; andforming a source region and a drain region based on the secondprotruding fin, wherein the gate stack is between the source region andthe drain region. In an embodiment, after the recessing, the secondprotruding fin has a height smaller than both of a first depth of thefirst isolation region and a second depth of the second isolationregion. In an embodiment, the first spacing and the second spacing havea difference smaller than about 4 nm. In an embodiment, the firstsemiconductor strip is a thin-and-tall fin having a first width at about5 nm below a top of the first semiconductor strip and a second width atabout 60 nm below the top of the first semiconductor strip, wherein thefirst width is smaller than about 5 nm, and the second width is smallerthan about 14.5 nm. In an embodiment, the second protruding fin is alsoan additional thin-and-tall fin. In an embodiment, the first isolationregion is comprised in a device die, and the device die comprises aplurality of FinFETs, and each of the plurality of the FinFETs comprisesan additional protruding fin and an additional isolation regionimmediately next to the additional protruding fin, and whereinthroughout an entirety of the device die, heights of all of theadditional protruding fins are smaller than depths of correspondingadditional isolation regions. In an embodiment, the forming the gatestack comprises forming a dummy gate stack on the first protruding fin;and replacing the dummy gate stack with a replacement gate stack. In anembodiment, the forming the dummy gate stack comprises depositing adummy gate electrode layer on the first protruding fin; forming amandrel over the dummy gate electrode layer; forming spacers on oppositesidewalls of the mandrel; removing the mandrel; and etching the dummygate electrode layer using the spacers as an etching mask, wherein aremaining part of the dummy gate electrode layer forms a part of thegate stack. In an embodiment, the filling the first trench and thesecond trench are filled using trisilylamine as a precursor. In anembodiment, the recessing the first isolation region results in a topsurface of the first isolation region to be curved, with a middleportion of the top surface being lower than edge portions of the topsurface, and wherein a depth of the first isolation region is measuredfrom the middle portion of the top surface.

In accordance with some embodiments of the present disclosure, a methodcomprises etching a semiconductor substrate to form a first trenchbetween a first semiconductor strip and a second semiconductor strip,wherein the first semiconductor strip has a first width at about 5 nmbelow a top of the first semiconductor strip and a second width at about60 nm below the top of the first semiconductor strip, wherein the firstwidth is smaller than about 5 nm, and the second width is smaller thanabout 14.5 nm; filling the first trench with dielectric materials toform a first isolation region; and recessing the first isolation region,with the first isolation region having a first depth after therecessing, wherein a first top portion of the first semiconductor stripprotrudes higher than the first isolation region to form a firstprotruding fin, and the first protruding fin has a first height smallerthan the first depth; and forming a gate stack extending on a sidewalland a top surface of the first protruding fin. In an embodiment, therecessing the first isolation region results in a top portion of thesecond semiconductor strip to protrude higher than the first isolationregion and to form a second protruding fin, and the second protrudingfin has a second height smaller than the first depth. In an embodiment,after the recessing, a second top portion of the second semiconductorstrip protrudes higher than the first isolation region to form a secondprotruding fin, and wherein after the gate stack is formed, a bendingvalue of the first protruding fin and the second protruding fin issmaller than about 4 nm. In an embodiment, the method further comprisesforming a second isolation region between and contacting the secondsemiconductor strip and a third semiconductor strip, with a top portionof the third semiconductor strip protruding higher than the secondisolation region to form a third protruding fin, and wherein the firstprotruding fin is spaced apart from the second protruding fin by a firstspacing, and the second protruding fin is spaced apart from the thirdprotruding fin by a second spacing, and wherein a difference between thefirst spacing and the second spacing is smaller than about 4 nm, andwherein an additional bending value of the second protruding fin and thethird protruding fin is smaller than 4 nm. In an embodiment, the secondisolation region has a second depth, and the third protruding fin has athird height smaller than the second depth. In an embodiment, the firstisolation region is comprised in a device die, and the device diecomprises a plurality of FinFETs, and each of the plurality of theFinFETs comprises an additional protruding fin and an additionalisolation region immediately next to the additional protruding fin, andwherein throughout an entirety of the device die, heights of all of theadditional protruding fins are smaller than depths of correspondingadditional isolation regions. In an embodiment, the forming the gatestack comprises forming a dummy gate stack on the first protruding fin;and replacing the dummy gate stack with a replacement gate stack. In anembodiment, the forming the dummy gate stack comprises depositing adummy gate electrode layer on the first protruding fin; forming amandrel over the dummy gate electrode layer; forming spacers on oppositesidewalls of the mandrel; removing the mandrel; and etching the dummygate electrode layer using the spacers as an etching mask, wherein aremaining part of the dummy gate electrode layer forms a part of thegate stack. In an embodiment, the filling the first trench with thedielectric materials is performed using trisilylamine as a precursor. Inan embodiment, the recessing the isolation region results in a topsurface of the first isolation region to be curved, with a middleportion of the top surface being lower than edge portions of the topsurface, and wherein the first depth is measured from the middle portionof the top surface.

In accordance with some embodiments of the present disclosure, anintegrated circuit structure comprises a first protruding fin having afirst width at about 5 nm below a first top of the first protruding finand a second width at about 60 nm below the first top of the firstprotruding fin, wherein the first width is smaller than about 5 nm, andthe second width is smaller than about 14.5 nm; a second protruding finhaving a third width at about 5 nm below a second top of the secondprotruding fin and a fourth width at about 60 nm below the second top ofthe second protruding fin, wherein the third width is smaller than about5 nm, and the fourth width is smaller than about 14.5 nm; and a firstshallow trench isolation region between the first protruding fin and thesecond protruding fin, wherein the first shallow trench isolation regionhas a depth, and wherein a first fin height of the first protruding finis smaller than the depth, and a bending value of the first protrudingfin and the second protruding fin is smaller than 4 nm. In anembodiment, the first fin height is measured from the first top of thefirst protruding fin to a lowest end of a top surface of the firstshallow trench isolation region. In an embodiment, the first protrudingfin is comprised in a device die, and the device die comprises aplurality of FinFETs, and each of the plurality of the FinFETs comprisesan additional protruding fin and an additional isolation regionimmediately next to the additional protruding fin, and whereinthroughout an entirety of the device die, heights of all of theadditional protruding fin are smaller than depths of correspondingadditional isolation regions. In an embodiment, the first protruding finis a silicon fin. In an embodiment, the first protruding fin comprisessilicon germanium. In an embodiment, the integrated circuit structurefurther comprises a third protruding fin; and a second isolation regionbetween the second protruding fin and the third protruding fin, whereinthe first protruding fin is spaced apart from the second protruding finby a first spacing, and the second protruding fin is spaced apart fromthe third protruding fin by a second spacing, and wherein a differencebetween the first spacing and the second spacing is smaller than about 4nm, and wherein an additional bending value of the second protruding finand the third protruding fin is smaller than about 4 nm. In anembodiment, a top surface of the first shallow trench isolation regionis curved, with a middle portion of the top surface being lower thanedge portions of the top surface, and wherein the depth is measured atthe middle portion.

In accordance with some embodiments of the present disclosure, anintegrated circuit structure comprises a bulk semiconductor substrate; afirst protruding fin, a second protruding fin, and a third protrudingfin adjacent to each other, with the second protruding fin being betweenthe first protruding fin and the second protruding fin, wherein thefirst protruding fin is spaced apart from the second protruding fin by afirst spacing, and the second protruding fin is spaced apart from thethird protruding fin by a second spacing, and wherein a differencebetween the first spacing and the second spacing is smaller than about 4nm; a first isolation region over the bulk semiconductor substrate andbetween the first protruding fin and the second protruding fin; and asecond isolation region over the bulk semiconductor substrate andbetween the second protruding fin and the third protruding fin, andwherein a bending value of the second protruding fin and the thirdprotruding fin is smaller than about 4 nm. In an embodiment, a firstheight of the first isolation region is greater than a depth of thefirst isolation region. In an embodiment, a first height of the firstisolation region is smaller than a depth of the first isolation region.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method comprising: etching a semiconductorsubstrate to form a first trench between a first semiconductor strip anda second semiconductor strip, and a second trench between the secondsemiconductor strip and a third semiconductor strip, wherein the secondtrench is deeper than the first trench; filling the first trench and thesecond trench to form a first isolation region between the firstsemiconductor strip and the second semiconductor strip, and a secondisolation region between the second semiconductor strip and the thirdsemiconductor strip; recessing the first isolation region and the secondisolation region, wherein a first protruding fin, a second protrudingfin, and a third protruding fin are formed as top portions of the firstsemiconductor strip, the second semiconductor strip, and the thirdsemiconductor strip, wherein the first protruding fin is spaced apartfrom the second protruding fin by a first spacing, and the secondprotruding fin is spaced apart from the third protruding fin by a secondspacing substantially equal to the first spacing, wherein bending valuesof the first protruding fin, the second protruding fin, and the thirdprotruding fin are smaller than about 4 nm; forming a gate stack on thesecond protruding fin; and forming a source region and a drain regionbased on the second protruding fin, wherein the gate stack is betweenthe source region and the drain region.
 2. The method of claim 1,wherein after the recessing, the second protruding fin has a heightsmaller than both of a first depth of the first isolation region and asecond depth of the second isolation region.
 3. The method of claim 1,wherein the first spacing and the second spacing have a differencesmaller than about 4 nm.
 4. The method of claim 1, wherein the firstsemiconductor strip is a thin-and-tall fin having a first width at about5 nm below a top of the first semiconductor strip and a second width atabout 60 nm below the top of the first semiconductor strip, wherein thefirst width is smaller than about 5 nm, and the second width is smallerthan about 14.5 nm.
 5. The method of claim 4, wherein the secondprotruding fin is also an additional thin-and-tall fin.
 6. The method ofclaim 1, wherein the first isolation region is comprised in a devicedie, and the device die comprises a plurality of Fin Field-EffectTransistors (FinFETs), and each of the plurality of the FinFETscomprises an additional protruding fin and an additional isolationregion immediately next to the additional protruding fin, and whereinthroughout an entirety of the device die, heights of all of theadditional protruding fins are smaller than depths of correspondingadditional isolation regions.
 7. The method of claim 1, wherein theforming the gate stack comprises: forming a dummy gate stack on thefirst protruding fin; and replacing the dummy gate stack with areplacement gate stack.
 8. The method of claim 7, wherein the formingthe dummy gate stack comprises: depositing a dummy gate electrode layeron the first protruding fin; forming a mandrel over the dummy gateelectrode layer; forming spacers on opposite sidewalls of the mandrel;removing the mandrel; and etching the dummy gate electrode layer usingthe spacers as an etching mask, wherein a remaining part of the dummygate electrode layer forms a part of the gate stack.
 9. The method ofclaim 1, wherein the filling the first trench and the second trench arefilled using trisilylamine as a precursor.
 10. The method of claim 1,wherein the recessing the first isolation region results in a topsurface of the first isolation region to be curved, with a middleportion of the top surface being lower than edge portions of the topsurface, and wherein a depth of the first isolation region is measuredfrom the middle portion of the top surface.
 11. An integrated circuitstructure comprising: a first protruding fin having a first width atabout 5 nm below a first top of the first protruding fin and a secondwidth at about 60 nm below the first top of the first protruding fin,wherein the first width is smaller than about 5 nm, and the second widthis smaller than about 14.5 nm; a second protruding fin having a thirdwidth at about 5 nm below a second top of the second protruding fin anda fourth width at about 60 nm below the second top of the secondprotruding fin, wherein the third width is smaller than about 5 nm, andthe fourth width is smaller than about 14.5 nm; and a first shallowtrench isolation region between the first protruding fin and the secondprotruding fin, wherein the first shallow trench isolation region has adepth, and wherein a first fin height of the first protruding fin issmaller than the depth, and a bending value of the first protruding finand the second protruding fin is smaller than 4 nm.
 12. The integratedcircuit structure of claim 11, wherein the first fin height is measuredfrom the first top of the first protruding fin to a lowest end of a topsurface of the first shallow trench isolation region.
 13. The integratedcircuit structure of claim 11, wherein the first protruding fin iscomprised in a device die, and the device die comprises a plurality ofFin Field-Effect Transistors (FinFETs), and each of the plurality of theFinFETs comprises an additional protruding fin and an additionalisolation region immediately next to the additional protruding fin, andwherein throughout an entirety of the device die, heights of all of theadditional protruding fin are smaller than depths of correspondingadditional isolation regions.
 14. The integrated circuit structure ofclaim 11, wherein the first protruding fin is a silicon fin.
 15. Theintegrated circuit structure of claim 11, wherein the first protrudingfin comprises silicon germanium.
 16. The integrated circuit structure ofclaim 11 further comprising: a third protruding fin; and a secondisolation region between the second protruding fin and the thirdprotruding fin, wherein the first protruding fin is spaced apart fromthe second protruding fin by a first spacing, and the second protrudingfin is spaced apart from the third protruding fin by a second spacing,and wherein a difference between the first spacing and the secondspacing is smaller than about 4 nm, and wherein an additional bendingvalue of the second protruding fin and the third protruding fin issmaller than about 4 nm.
 17. The integrated circuit structure of claim11, wherein a top surface of the first shallow trench isolation regionis curved, with a middle portion of the top surface being lower thanedge portions of the top surface, and wherein the depth is measured atthe middle portion.
 18. An integrated circuit structure comprising: abulk semiconductor substrate; a first protruding fin, a secondprotruding fin, and a third protruding fin adjacent to each other, withthe second protruding fin being between the first protruding fin and thesecond protruding fin, wherein the first protruding fin is spaced apartfrom the second protruding fin by a first spacing, and the secondprotruding fin is spaced apart from the third protruding fin by a secondspacing, and wherein a difference between the first spacing and thesecond spacing is smaller than about 4 nm; a first isolation region overthe bulk semiconductor substrate and between the first protruding finand the second protruding fin; and a second isolation region over thebulk semiconductor substrate and between the second protruding fin andthe third protruding fin, and wherein a bending value of the secondprotruding fin and the third protruding fin is smaller than about 4 nm.19. The integrated circuit structure of claim 18, wherein a first heightof the first isolation region is greater than a depth of the firstisolation region.
 20. The integrated circuit structure of claim 18,wherein a first height of the first isolation region is smaller than adepth of the first isolation region.